Semiconductor device and manufacturing method thereof

ABSTRACT

In order to improve the reliability of a semiconductor device, dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form a pad, a first side nearest to a corner; and a second dummy part provided to be spaced apart from and to be parallel to, of the sides that form the pad, a second side nearest to an edge side of a semiconductor chip. That is, the dummy wiring is formed by: a first dummy part extending along the first side of the pad; and a second dummy part extending along the second side of the pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2014-045679 filed onMar. 7, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and amanufacturing technique thereof, and for example, to a technologyeffective in applying to a semiconductor device having pads and amanufacturing technique thereof.

Japanese Unexamined Patent Application Publication No. 2003-45876describes a technique for forming dummy wiring around a pad.

Japanese Unexamined Patent Application Publication No. Hei 5(1993)-235085 describes a technique for providing a dummy pad exposedfrom a cover film so as to surround a bonding pad.

Japanese Unexamined Patent Application Publication No. 2010-10197describes a technique for providing, in a corner of a semiconductorchip, a small pad to be used exclusively for a probe.

SUMMARY

For example, in a pad formed in a semiconductor chip, an end portion ofthe pad is covered with a surface protective film, while most of thesurface of the pad is exposed from an opening provided in the surfaceprotective film. That is, in the end portion of the pad, the surfaceprotective film is formed to cover a level difference resulting from thethickness of the pad.

Herein, a crack may occur in the surface protective film, covering alevel difference formed in the end portion of the pad, by the stressapplied when dicing for cutting semiconductor chips into pieces isperformed, or the stress applied from a sealing body for sealing asemiconductor chip, etc. In particular, for a pad arranged near a cornerof a semiconductor chip having a rectangular shape, there is thetendency that a crack is likely to occur in a surface protective filmcovering a level difference formed in an end portion of the pad. Thatis, because stress is likely to be applied in a corner of asemiconductor chip, occurrence of a crack is likely to become obvious ina surface protective film covering a level difference formed in an endportion of a pad. From the fact described above, there is room forimprovement in the current semiconductor devices, from the viewpoint ofimproving the reliability of a semiconductor device by suppressingoccurrence of a crack in a surface protective film covering a leveldifference formed in an end portion of a pad.

Other problems and new characteristics will become clear from thedescription and accompanying drawings of the present specification.

A semiconductor device according to one embodiment has dummy wiringprovided around a first pad arranged at a position nearest to a cornerof a semiconductor chip. In this case, the dummy wiring includes: afirst dummy part provided to be spaced apart from and to be parallel to,of a plurality of sides that form the first pad, a first side nearest tothe corner of the semiconductor chip; and a second dummy part providedto be spaced apart from and to be parallel to a second side nearest toan edge side of the semiconductor chip.

A method of manufacturing a semiconductor device according to oneembodiment includes the steps of: forming a plurality of pads eachhaving a rectangular shape along a boundary line between a chip regionand a scribe region and within the chip region; and forming dummy wiringaround, of the pads, a first pad nearest to a corner of the chip region.In this case, the dummy wiring includes: a first dummy part provided tobe spaced apart from and to be parallel to, of a plurality of sides thatform the first pad, a first side nearest to a corner of a semiconductorchip; and a second dummy part provided to be spaced apart from and to beparallel to a second side nearest to an edge side of the semiconductorchip.

According to one embodiment, the reliability of a semiconductor devicecan be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device including a QFP package,when viewed from upside;

FIG. 2 is a sectional view, taken along A-A line in FIG. 1;

FIG. 3 is a view illustrating a layout configuration of a semiconductorchip;

FIG. 4 is a sectional view illustrating a structure of a near-fieldregion of a pad including the pad;

FIG. 5 is a view for explaining a mechanism of occurrence of “aluminumslide”;

FIG. 6 is a view for explaining a mechanism of occurrence of “aluminumslide”;

FIG. 7 is a view for explaining a mechanism of occurrence of “aluminumslide”;

FIG. 8 is a view illustrating a layout configuration of a semiconductorchip according to an embodiment;

FIG. 9 is an enlarged view in which a partial region of FIG. 8 isenlarged;

FIG. 10 is a sectional view, taken along A-A line in FIG. 9;

FIG. 11 is a schematic sectional view, taken along B-B line in FIG. 9;

FIG. 12 is a sectional view illustrating, in a semiconductor deviceaccording to an embodiment, a structure of a pad and a peripherythereof, the pad being arranged at a position nearest to a corner of asemiconductor chip;

FIG. 13 is a plan view illustrating a layout configuration of asemiconductor wafer;

FIG. 14 is a sectional view illustrating a step of manufacturing asemiconductor device according to an embodiment;

FIG. 15 is a sectional view illustrating a step of manufacturing thesemiconductor device following FIG. 14;

FIG. 16 is a sectional view illustrating a step of manufacturing thesemiconductor device following FIG. 15;

FIG. 17 is a sectional view illustrating a step of manufacturing thesemiconductor device following FIG. 16;

FIG. 18 is a sectional view illustrating a step of manufacturing thesemiconductor device following FIG. 17;

FIG. 19 is a sectional view illustrating a step of manufacturing thesemiconductor device following FIG. 18;

FIG. 20 is a schematic sectional view illustrating a periphery of aboundary region between a chip region and a scribe region after a pad isformed;

FIG. 21 is a flow chart showing the flow of steps of manufacturing asemiconductor device including a QFP package after an integrated circuitis formed in a semiconductor wafer;

FIG. 22 is a schematic view illustrating First Variation of theembodiment, the view corresponding to an enlarged view in which thepartial region of FIG. 8 is enlarged;

FIG. 23 is a schematic view illustrating Second Variation of theembodiment, the view corresponding to an enlarged view in which thepartial region of FIG. 8 is enlarged;

FIG. 24 is a schematic view illustrating Third Variation of theembodiment, the view corresponding to an enlarged view in which thepartial region of FIG. 8 is enlarged;

FIG. 25 is a schematic view illustrating Fourth Variation of theembodiment, the view corresponding to an enlarged view in which thepartial region of FIG. 8 is enlarged; and

FIG. 26 is a schematic view illustrating Fifth Variation of theembodiment.

DETAILED DESCRIPTION

When necessary for convenience in the following embodiment, descriptionis given by dividing the embodiment into a plurality of sections orembodiments, however, unless stated explicitly, they are not independentof one another, but one is related with the other part or the whole as amodification example, a detail, supplementary description, etc.

When referring to the number of elements, etc. (including number ofpieces, numerical value, quantity, range, etc.) in the followingembodiment, unless stated explicitly or except when the number isobviously limited to specific numbers in principle, the number is notlimited to the specific ones but may be more or less than the specificnumbers.

Further, in the following embodiment, it is needless to say thatcomponents (also including constituent steps, etc.) are not necessarilyrequisite unless stated explicitly or except when they are obviouslyrequisite in principle.

Similarly, when referring to the shapes and positional relations, etc.,of components, etc., in the following embodiment, unless statedexplicitly or except when they can be thought otherwise in principle,those substantially the same or similar to the shapes, etc., are to beincluded. This also applies to the aforementioned numerical values andranges.

In addition, like components are denoted with like reference numerals inprinciple in each of the views for explaining embodiments, andduplicated descriptions are omitted. For easy understanding of drawings,hatching lines are sometimes drawn even in a plan view.

Embodiment Example of Configuration of Semiconductor Device (QFPPackage)

There are various types of package structures of semiconductor devices,such as, for example, a BGA (Ball Grid Array) package and a QFP (QuadFlat Package) package. The technical ideas of the present embodimentscan be applied to these packages, and hereinafter a configuration of asemiconductor device including a QFP package will be described as anexample.

FIG. 1 is a plan view of a semiconductor device SA1 including a QFPpackage, when viewed from upside. As illustrated in FIG. 1, thesemiconductor device SA1 has a rectangular shape, and the upper surfaceof the semiconductor device SA1 is covered with a resin (sealing body)MR. Outer leads OL protrude toward the outside from four sides by whichthe outer shape of the resin MR is defined.

Subsequently, the internal structure of the semiconductor device SA1will be described. FIG. 2 is a sectional view, taken along A-A line inFIG. 1. As illustrated in FIG. 2, the rear surface of a chip mountingpart TAB is covered with the resin MR. On the other hand, asemiconductor chip CHP is mounted over the upper surface of the chipmounting part TAB, and the chip mounting part TAB is separated from aninner lead IL1 (lead terminal). A pad PD is formed in the main surfaceof the semiconductor chip CHP. The pad PD, formed in the semiconductorchip CHP, is electrically coupled to the inner lead IL1 by a wire W. Thesemiconductor chip CHP, the wire W, and the inner lead IL1 are coveredwith the resin MR, and the outer lead OL (lead terminal), integratedwith the inner lead IL1, protrudes from the resin MR. The outer lead OL,protruding from the resin MR, is formed into a gull-wing shape, and ametal-plated film PF is formed over the surface of the outer lead OL.

The chip mounting part TAB, the inner lead IL1, and the outer lead OLare formed, for example, of a copper material, 42 Alloy (alloy of ironand nickel), or the like, while the wire W is formed, for example, of agold wire. The semiconductor chip CHP is formed, for example, of siliconor a compound semiconductor (GaAs, etc.), and a plurality ofsemiconductor elements, such as MOSFETs, are formed in thissemiconductor chip CHP. Multilayer wiring is formed above thesemiconductor elements via an interlayer insulating film, and a pad PDto be coupled to the multilayer wiring is formed in the uppermost layerof the multilayer wiring. Accordingly, the semiconductor elements formedin the semiconductor chip CHP are electrically coupled to the pad PD viathe multilayer wiring. That is, an integrated circuit is formed by thesemiconductor elements, formed in the semiconductor chip CHP, and themultilayer wiring, and the pad PD functions as a terminal for couplingthe integrated circuit and the outside of the semiconductor chip CHPtogether. The pad PD is coupled to the inner lead IL1 by the wire W, andis also coupled to the outer lead OL formed integrally with the innerlead IL1. From this, it is known that the integrated circuit, formed inthe semiconductor chip CHP, can be electrically coupled to the outsideof the semiconductor device SA1 by a pathway including the pad PD, thewire W, the inner lead IL1, the outer lead OL, and an external couplingdevice in this order. That is, it is known that the integrated circuit,formed in the semiconductor chip CHP, can be controlled by inputting anelectrical signal from the outer lead OL formed in the semiconductordevice SA1. It is also known that an output signal from the integratedcircuit can be taken out from the outer lead OL to the outside.

Subsequently, FIG. 3 is a view illustrating a layout configuration ofthe semiconductor chip CHP. In FIG. 3, the semiconductor chip CHP has,for example, a rectangular shape, and a plurality of the pads PD arearranged along an edge side of the semiconductor chip CHP. In each ofthese pads PD, an end portion of the pad PD is covered with a surfaceprotective film, while most of the surface of the pad PD is exposed froman opening provided in the surface protective film, although they arenot illustrated in FIG. 3.

Herein, a crack may occur in the surface protective film, covering theend portion of the pad PD, by stress applied when dicing, for cuttingthe semiconductor chips CHP into pieces, is performed, or stress appliedfrom the resin (sealing body) for sealing the semiconductor chip CHP,etc. In particular, there is the tendency that a crack is likely tooccur in the surface protective film in a peripheral region R1 of a padPD1 arranged to be nearest to a corner CNR of the semiconductor chipCHP, as illustrated, of FIG. 3, in an enlarged view of a region A1 thatis a region near a corner of the semiconductor chip CHP. That is, stressis likely to be applied in the corner CNR of the semiconductor chip CHP,and hence occurrence of a crack becomes obvious in the surfaceprotective film covering the end portion of the pad PD1 arranged to benearest to the corner CNR. Accordingly, there is room for improvement ina semiconductor device in which the semiconductor chip CHP is sealedwith a resin, from the viewpoint of suppressing occurrence of a crack inthe surface protective film covering the end portion of the pad PD1arranged to be nearest to the corner CNR. Hereinafter, details of theroom for improvement will be described.

<Room for Improvement> FIG. 4 is a sectional view illustrating astructure of a near-field region of the pad PD including the pad PD. ASillustrated in FIG. 4, a surface protective film PAS, including alaminated film, for example, of a silicon oxide film OXF and a siliconnitride film SNF, is formed to cover the pad PD including, for example,aluminum as a major component. An opening OP is formed in this surfaceprotective film PAS, and part of the surface of the pad PD is exposedfrom the bottom of this opening OP. On the other hand, the end portionof the pad PD is covered with the surface protective film PAS. That is,in the end portion of the pad PD, the surface protective film PAS isformed to cover a level difference resulting from the thickness of thepad PD. Further, the wire W including, for example, a gold wire iscoupled to the surface of the pad PD exposed from the opening OP, andthe surface protective film PAS, including the surface of the pad PD towhich the wire W is coupled, is covered, for example, with the resin MR.

When attention is focused on a region B1 illustrated in FIG. 4, it isknown that the covering shape of the surface protective film PAS becomesprecipitous due to a level difference generated by the thickness of thepad PD and that the thickness of the surface protective film PAS in theregion B1 becomes small. This means that the stress from the resin MR,sealing the surface protective film PAS, becomes large in the region B1where the covering shape of the surface protective film PAS becomesprecipitous and the thickness of the surface protective film PAS becomessmall. That is, in the region B1 where the covering shape of the surfaceprotective film PAS becomes precipitous and the thickness of the surfaceprotective film PAS becomes small, large stress is applied from theresin MR, and as a result thereof, a crack is likely to occur in thesurface protective film PAS, as illustrated in FIG. 5. In particular,the stress applied from the resin is likely to be large in the cornerCNR of the semiconductor chip CHP illustrated in FIG. 3, and henceoccurrence of a crack is likely to be obvious in the peripheral regionR1 of the surface protective film covering the end portion of the pad PD(PD1) arranged to be nearest to the corner CNR.

Moreover, semiconductor elements represented by a field-effecttransistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor)and the wiring to be coupled to the semiconductor elements are recentlybeing miniaturized. With such miniaturization of the semiconductorelements and the wiring being developed, there is the tendency that thethickness of the pad PD becomes large. It is because the development ofthe generations of the miniaturization of the semiconductor elements andthe wiring actually means that an integrated circuit formed in thesemiconductor chip CHP is highly integrated, and thereby an amount ofthe current to be used in the semiconductor chip CHP is increased,although it is superficially thought that, with the aforementioneddevelopment, the thickness of the pad PD is also made small. That is, anincrease in the amount of current to be used in the semiconductor chipCHP means that a large current flows through the pad PD coupled to ahighly integrated circuit, which requires the thickness of the pad PD tobe made large, because the resistance of the pad PD needs to be made aslow as possible. From this, there is the tendency that the thickness ofthe pad PD becomes large, with the development of the generations ofminiaturization. This means that a level difference, resulting from thethickness of the pad PD, becomes large in a product manufactured in adeveloped generation of miniaturization. Thereby, it can be consideredthat precipituousness of the covering shape of the surface protectivefilm PAS and thinning of the thickness of the surface protective filmPAS may become remarkable in the region B1 illustrated, for example, inFIG. 4.

From the facts described above, it can be considered that: the stressapplied from the resin MR to the region B1 of the surface protectivefilm PAS, covering the end portion of the pad PD arranged to be nearestto the corner CNR of the semiconductor chip CHP, becomes large in aproduct manufactured in a developed generation of miniaturization; andas a result thereof, occurrence of a crack CLK in the surface protectivefilm PAS becomes more obvious. That is, it can be considered that, in aproduct manufactured in a more developed generation of miniaturizationand in the pad PD arranged to be nearest to the corner CNR of thesemiconductor chip CHP, the crack CLK is more likely to occur in thesurface protective film PAS, due to a level difference resulting fromthe thickness of the pad PD, and hence it becomes more necessary tosuppress occurrence of a crack CLK in the surface protective film PAS.

When the crack CLK occurs in the surface protective film PAS asillustrated in FIG. 5, a phenomenon, which is referred to as so-called“aluminum slide”, occurs by a heat cycle test performed after a productis completed, in which the positions of part of the pads PD are shifted.Specifically, in the heat cycle test, the reliability of a semiconductordevice is checked by repeatedly changing a temperature, for example,between −65° C. and 150° C. In this case, when a temperature isrepeatedly changed in a state where the crack CLK occurs in the surfaceprotective film PAS, as illustrated in FIG. 6, the positions of part ofthe pads PD are shifted, as illustrated in FIG. 7, by the stressresulting from expansion and contraction of the resin MR based on thetemperature change, which causes the “aluminum slide”. If such “aluminumslide” occurs, the positions of part of the pads PD are shifted fromnormal positions, which may causes an appearance defect of the pad PD.Accordingly, in order to suppress an appearance defect of the pad PD, itis necessary to suppress “aluminum slide” that is a phenomenon in whichthe position of the pad PD is shifted. Because the “aluminum slide”occurs by occurrence of the crack CLK in the surface protective filmPAS, it is necessary to suppress occurrence of the crack CLK in thesurface protective film PAS, in order to suppress an appearance defectof the pad PD.

Accordingly, a device is incorporated in the present embodiment, inwhich occurrence of the crack CLK in the surface protective film PAS,resulting from a level difference occurring due to the thickness of thepad PD, is suppressed. Hereinafter, the technical ideas of the presentembodiment incorporating this device will be described.

<Configuration of Semiconductor Chip> FIG. 8 is a view illustrating alayout configuration of the semiconductor chip CHP according to thepresent embodiment. In FIG. 8, the semiconductor chip CHP has, forexample, a rectangular shape, and a plurality of the pads PD, eachincluding aluminum as a major component, are arranged along an edge sideof the semiconductor chip CHP. In each of these pads PD, an end portionof the pad PD is covered with a surface protective film, while most ofthe surface of the pad PD is exposed from an opening provided in thesurface protective film, although they are not illustrated in FIG. 8.

As used herein, the “major component” means, of constituent materialsthat form members (layers and films), a material component that isincluded in the largest amount, and for example, the “pad PD includingaluminum as a major component” means that the material for the pad PDincludes aluminum (Al) in the largest amount. In the presentspecification, the term “major component” is intended to express that,for example, the pad PD is basically formed by aluminum but the casewhere impurities are also included is not excluded.

For example, when attention is focused on the pad PD generally used in asemiconductor device, this pad PD has a configuration in which analuminum film is usually sandwiched by barrier conductor films includinga titanium/titanium nitride film. That is, the pad PD including a firstbarrier conductor film, an aluminum film formed over the first barrierconductor film, and a second barrier conductor film formed over thealuminum film. In this case, when the pad PD is formed by a laminatedfilm including the first barrier conductor film, the aluminum film, andthe second barrier conductor film, this pad PD is referred to as the“pad PD including aluminum as a major component”, because the pad PD ismostly occupied by the aluminum film.

Additionally, the aluminum film as used herein is used to have a wideconcept including: an aluminum film having pure aluminum; an aluminumalloy film (AlSi film) having silicon added to aluminum; and an aluminumalloy film (AlSiCu film) having silicon and copper added to aluminum.The pads PD including these aluminum alloy films are also included inthe “pad PD including aluminum as a major component.” That is, the “padPD including aluminum as a major component” as used herein is applied tothe pad PD including an aluminum film and a barrier conductor film, andalso applied to the pad PD in which an aluminum film itself is analuminum alloy film.

Characteristics in Embodiment

Subsequently, characteristic points in the present embodiment will bedescribed. FIG. 9 is an enlarged view in which the region C1 of FIG. 8is enlarged. In FIG. 9, the semiconductor chip CHP has the edge side ES,and a plurality of the pads PD, each having a rectangular shape, arearranged along the edge side ES and in a region inside the edge side ES.In detail, a dummy region DMR is first formed in the region inside theedge side ES of the semiconductor chip CHP, and a seal ring region SRRis formed in a region inside the dummy region DMR. A dummy pattern forsuppressing procession of a crack, which may occur while dicing is beingperformed, into the semiconductor chip CHP (into a chip region) isprovided in the dummy region DMR, and a seal ring for suppressing aforeign substance from entering the inside of the semiconductor chip CHPis provided in the seal ring region SRR. Herein, the dummy pattern inthe dummy region DMR is not always necessary. However, it is preferableto provide the dummy pattern for prevention of the aforementioned crackor for improvement in the flatness for a CMP step performed when eachwiring layer is formed.

For simple description, the dummy region DMR is described as part of thesemiconductor chip CHP in the present embodiment. However, the dummyregion DMR is a region integrated with the scribe region SCR in a waferstate before dicing is performed. Accordingly, the dummy region DMR maybe expressed as part of the scribe region SCR in the later description.

The pads PD are arranged in a region inside the seal ring region SRR. Ofthe pads PD, the pad arranged at a position nearest to the corner CNR ofthe semiconductor chip CHP is referred to as a pad PD 1 in the presentspecification.

As illustrated in FIG. 9, the pad PD1 arranged at a position nearest tothe corner CNR of the semiconductor chip CHP has a rectangular shape,and dummy wiring DML is provided around the pad PD1. The presentembodiment is characterized by the fact that the dummy wiring DML isthus provided around the pad PD1. Specifically, the dummy wiring DMLincludes: a dummy part DMP1 provided to be spaced apart from and to beparallel to, of a plurality of sides that form the pad PD1, a side SD1nearest to the corner CNR; and a dummy part DMP2 provided to be spacedapart from and to be parallel to, of the sides that form the pad PD1, aside SD2 nearest to the edge side ES of the semiconductor chip CHP, asillustrated in FIG. 9. That is, the dummy wiring DML is formed by thedummy part DMP1 extending along the side SD1 of the pad PD1 1 and thedummy part DMP2 extending along the side SD2 of the pad PD1. The dummypart DMP1 and the dummy part DMP2 are formed integrally with each other,and have, for example, an L-shape in plan view.

Subsequently, FIG. 10 is a sectional view, taken along A-A line in FIG.9. As illustrated in FIG. 10, a field-effect transistor Q, an example ofa semiconductor element, is formed over a semiconductor substrate 1Sincluding, for example, silicon, and a fine layer FL including, forexample, fine copper wiring is formed over the field-effect transistorQ. A global layer GL, including copper wiring having a width lager thanthat of the copper wiring that forms the fine layer FL, is formed overthe fine layer FL. The pad PD1 is formed over the global layer GL, andthe pad PD1 and the global layer GL form the dummy wiring DML. In thiscase, the level of the surface of the dummy wiring DML is the same asthat of the surface of the pad PD1, as illustrated in FIG. 10.

Herein, the pad PD1 is electrically coupled to the field-effecttransistor Q formed over the semiconductor substrate 1S via the globallayer GL and the fine layer FL, as illustrated in FIG. 10. On the otherhand, the dummy wiring DML is not electrically coupled to thefield-effect transistor Q, which is a semiconductor element, and hencedose not function as usual wiring (actual wiring) to be used fortransmission of an electrical signal or for supply of power supplyvoltage, etc. That is, the pad PD1 forms part of an integrated circuit,while the dummy wiring DML does not form part of the integrated circuit.From this, the potential of the dummy wiring DML is, for example, in afloating state.

Subsequently, the surface protective film PAS is formed to cover the padPD1 and the dummy wiring DML, which are formed in the same layer. Thesurface protective film PAS is formed of a laminated film including, forexample, the silicon oxide film OXF and the silicon nitride film SNF.The opening OP is formed in the surface protective film PAS, and part ofthe surface of the pad PD is exposed from the bottom of the opening OP.On the other hand, an opening is not formed over the dummy wiring DML,and the dummy wiring DML is covered with the surface protective filmPAS.

The wire W including, for example, a gold wire is coupled to the surfaceof the pad PD exposed from the opening OP, and the surface protectivefilm PAS, including the surface of the pad PD1 to which the wire W iscoupled, is covered, for example, with the resin MR.

Subsequently, FIG. 11 is a schematic sectional view, taken along B-Bline in FIG. 9. As illustrated in FIG. 11, the dummy region DMR isprovided inside the edge side ES of the semiconductor chip CHP, and thedummy pattern DP is formed in the dummy region DMR. The seal ring regionSRR is provided inside the dummy region DMR, and the seal ring SRG isformed in the seal ring region SRR. Further, a region inside the sealring region SRR serves as an integrated circuit region ICR, and the padPD1 and the dummy wiring DML, which are formed in the same layer, areformed in the integrated circuit region ICR. In this case, the dummywiring DML is only provided between the pad PD1 and the seal ring SRGand there is no wiring to be electrically coupled to the semiconductorelement in the present embodiment. That is, actual wiring that forms theintegrated circuit is not formed between the pad PD1 and the seal ringSRG.

The seal ring SRG disclosed in the present embodiment is formed bycoupling a multilayer wiring layer, and is coupled to the semiconductorsubstrate 1S. Although not illustrated in detail, the seal ring SRG iscoupled to a well formed in the semiconductor substrate 1S to have afixed potential, such as a ground potential, etc. On the other hand, thedummy pattern DP is formed by a multilayer wiring layer, similarly tothe seal ring SRG, and respective wiring layers may be coupled togetheror separated from each other. Unlike the seal ring SRG, the dummypattern DP is not coupled to a fixed potential and is in a floatingstate.

As illustrated in FIG. 11, the surface protective film PAS, includingthe silicon oxide film OXF and the silicon nitride film SNF, is furtherformed to cover the pad PD1 and the dummy wiring DML, which are formedin the same layer. The opening OP is formed in the surface protectivefilm PAS, and part of the surface of the pad PD1 is exposed from thebottom of the opening OP, while the dummy wiring DML is covered with thesurface protective film PAS. The surface protective film PAS is furtherformed to extend to the edge side ES of the semiconductor chip CHP bycovering the seal ring region SRR and the dummy region DMR, which areformed outside the integrated circuit region ICR.

Herein, a wiring structure and a device structure, which are formed inlayers lower than the pad PD1 and the dummy wiring DML formed in theintegrated circuit region ICR, are basically the same as those in FIG.10, and hence they are omitted in FIG. 11. Also, a wire to be coupled tothe pad PD1 and a resin covering the surface protective film PAS are notillustrated in FIG. 11.

As described above, the present embodiment is characterized by the factthat the dummy wiring DML is provided around the pad PD1 arranged at aposition nearest to the corner CNR of the semiconductor chip CHP, asillustrated, for example, in FIGS. 9 to 11. Further, the presentembodiment is characterized by the fact that the dummy wiring DML isformed to include: the dummy part DMP1 provided to be spaced apart fromand to be parallel to the side SD1 nearest to the corner CNR; and thedummy part DMP2 provided to be spaced apart from and to be parallel tothe side SD2 nearest to the edge side ES of the semiconductor chip CHP.Thereby, the remarkable effect that the reliability of a semiconductordevice can be improved can be acquired according to the presentembodiment. Specifically, the remarkable effect that, in a semiconductordevice in which a semiconductor chip is sealed by a resin, occurrence ofa crack in a surface protective film covering the end portion of the padPD1 arranged to be nearest to the corner CNR can be suppressed can beacquired according to the technical ideas of the present embodiment.Hereinafter, the reason why the aforementioned remarkable effect can beacquired according to the present embodiment will be described.

FIG. 12 is a sectional view illustrating, in a semiconductor deviceaccording to the present embodiment, a structure of the pad PD1 and aperiphery thereof, the pad PD1 being arranged at a position nearest to acorner of a semiconductor chip. AS illustrated in FIG. 12, a surfaceprotective film PAS, including a laminated film, for example, of asilicon oxide film OXF and a silicon nitride film SNF, is formed tocover the pad PD1 including aluminum as a major component. An opening OPis formed in the surface protective film PAS, and part of the surface ofthe pad PD1 is exposed from the bottom of the opening OP. On the otherhand, the end portion of the pad PD1 is covered with the surfaceprotective film PAS. Further, a wire W including, for example, a goldwire is coupled to the surface of the pad PD1 exposed from the openingOP, and the surface protective film PAS, including the surface of thepad PD1 to which the wire W is coupled, is covered, for example, with aresin MR. In the present embodiment, the dummy wiring DML is formed at aposition spaced apart from the pad PD1, and the surface protective filmPAS is formed to cover also the dummy wiring DML.

Herein, when attention is first focused on the region B1 in FIG. 4illustrating a pad structure in which the dummy wiring DML is notformed, it is known that the covering shape of the surface protectivefilm PAS becomes precipitous due to a level difference generated by thethickness of the pad PD1 and that the thickness of the surfaceprotective film PAS becomes small in the region B1. This means that thestress from the resin MR, sealing the surface protective film PAS,becomes large in the region B1 where the covering shape of the surfaceprotective film PAS becomes precipitous and the thickness of the surfaceprotective film PAS becomes small. That is, in the region B1 where thecovering shape of the surface protective film PAS becomes precipitousand the thickness of the surface protective film PAS becomes small,large stress is applied from the resin MR, and as a result thereof, acrack is likely to occur in the surface protective film PAS.

On the other hand, when attention is focused on the region D1 in FIG. 12illustrating a pad structure in which the dummy wiring DML is formed, itis known that, as a result that the dummy wiring DML is formed in anear-field region of the pad PD1, even if a level difference resultingfrom the thickness of the pad PD1 is generated, the precipitousness ofthe curving shape of the surface protective film PAS is made gentler andthe thickness of the surface protective film PAS in the region D1becomes larger than those in the region B1 in FIG. 4. This means thatthe stress from the resin MR that seals the surface protective film PASis suppressed in the region D1. That is, the stress from the resin MR issuppressed in the region D1 where the precipitousness of the curvingshape of the surface protective film PAS is made gentle and thethickness of the surface protective film PAS becomes large. As a resultthereof, a crack hardly occurs in the surface protective film PAScovering the end portion of the pad PD1, according to the presentembodiment.

According to the present embodiment, by thus providing the dummy wiringDML in a near-field region of the end portion of the pad PD1, theprecipitousness of the curving shape of the surface protective film PAS,covering the end portion of the pad PD1, can be made gentle and thethickness of the surface protective film PAS can be made large in theregion D1 of the surface protective film PAS, even if a level differenceresulting from the thickness of the pad PD1 is present in the region D1.That is, by providing the dummy wiring DML in a near-field region of theend portion of the pad PD1, stress resistance can be improved in theregion D1 to which the stress from the resin MR that seals the surfaceprotective film PAS is likely to be applied, according to the presentembodiment. As a result thereof, occurrence of a crack in the surfaceprotective film PAS can be suppressed in the region D1, according to thepresent embodiment, and thereby “aluminum slide”, which is likely tooccur when a heat cycle test is performed in a state where a crackoccurs in the surface protective film PAS, can be effectivelysuppressed. The fact that the “aluminum slide” can be suppressed meansthat an appearance defect of the pad PD1 can be reduced, and thereby thereliability of a semiconductor device can be improved according to thepresent embodiment.

There is the tendency that, with the generations of miniaturization ofboth semiconductor elements represented by a field-effect transistor andwiring being developed, the thickness of the pad PD1 becomes larger.This means that, in a product manufactured in a developed generation ofminiaturization, a level difference resulting from the thickness of thepad PD1 becomes large. Accordingly, it can be considered that, whenminiaturization of semiconductor elements and wiring is developed, theprecipitousness of the covering shape of the surface protective filmPAS, covering the end portion of the pad PD1, and the thinning of thethickness of the surface protective film PAS are likely to becomeobvious as problems. That is, with a product manufactured in a moredeveloped generation of miniaturization, a crack is more likely to occurin the surface protective film PAS, due to a level difference resultingfrom the thickness of the pad PD1. Accordingly, it can be consideredthat, in a product manufactured in a developed generation ofminiaturization, it becomes further important to suppress occurrence ofa crack in the surface protective film PAS.

Regarding this point, the dummy wiring DML is formed in a near-fieldregion of the pad PD1 in the present embodiment, and as a resultthereof, even if a level difference resulting from the thickness of thepad PD1 is generated, the precipitousness of the covering shape of thesurface protective film PAS, covering the end portion of the pad PD1, ismade gentle and the thickness of the surface protective film PAS becomeslarge. This phenomenon will be similarly generated, even if thethickness of the pad PD1 becomes large and a level difference resultingfrom the thickness of the pad PD1 becomes large, with the generations ofminiaturization of semiconductor elements and wiring being developed.From this, by forming the dummy wiring DML in a near-field region of thepad PD1, occurrence of a crack in the surface protective film PAS,covering the end portion of the pad PD1, can be effectively preventedaccording to the present embodiment, even if the generations ofminiaturization of semiconductor elements and wiring are developed and alevel difference resulting from the thickness of the pad PD1 becomeslarge. When the generations of miniaturization are developed and a leveldifference resulting from the thickness of the pad PD1 becomes large,namely, when occurrence of a crack is likely to become obvious, theavailability of applying the technical ideas of the present embodimentis increased. However, it is needless to say that the remarkable effectthat occurrence of a crack in the surface protective film PAS, coveringthe end portion of the pad PD1, is suppressed can be acquired by thetechnical ideas of the present embodiment, regardless of how large alevel difference resulting from the thickness of the pad PD1 is.

In the present embodiment, the dummy wiring DML is provided around thepad PD1 nearest to the corner CNR of the semiconductor chip CHP, asillustrated in FIG. 9. Specifically, the dummy part DMP1, extending tobe spaced apart from and along the side SD1 of the pad PD1, and thedummy part DMP2, extending to be spaced apart from and along the side2of the pad PD1, are provided. Thereby, in the pad PD1 nearest to thecorner CNR of the semiconductor chip CHP, to the pad PD1 stress beinglikely to be applied, occurrence of a crack in the surface protectivefilm, covering the end portion of the pad PD1, can be suppressed. Thatis, with attention focused on that stress is likely to be applied to thepad PD1 nearest to the corner CNR of the semiconductor chip CHP, thedummy wiring DML is provided around the pad PD1 in the presentembodiment, in order not to generate a crack in the surface protectivefilm covering the end portion of the pad PD1. Further, it is known that,in the pad PD1 nearest to the corner CNR of the semiconductor chip CHP,a crack is likely to occur particularly in the peripheral region R1 thatis: near to, of the sides that form the pad PD1, the side nearest to thecorner CNR; and near to the side nearest to the edge side of thesemiconductor chip CHP, as illustrated in FIG. 3. Accordingly, in viewof this, the dummy part DMP1, which is spaced apart from and to beparallel to, of the sides that form the pad1 nearest to the corner CNRof the semiconductor chip CHP, the side SD1 nearest to the corner CNR,and the dummy part DMP2, which is spaced apart from and to be parallelto the side SD2 nearest to the edge side ES of the semiconductor chipCHP, are provided in the present embodiment, as illustrated in FIG. 9.Thereby, occurrence of a crack in the surface protective film coveringthe end portion of the pad PD1 can be effectively suppressed accordingto the present embodiment.

On the other hand, the dummy wiring DML is not provided around the padsPD other than the pad PD1 nearest to the corner CNR of the semiconductorchip CHP in the present embodiment, as illustrated, for example, in FIG.9. This is because it is taken into consideration that, as describedabove, stress is likely to be applied particularly in the pad PD1nearest to the corner CNR of the semiconductor chip CHP and a crack islikely to occur in the surface protective film covering the end portionof the pad PD1. In other words, it is taken into consideration that: inthe pads PD other than the pad PD1 nearest to the corner CNR of thesemiconductor chip CHP, stress to be applied is smaller than that in thepad PD1; and occurrence of a crack in the surface protective film,covering the end portion of the pad PD, does not become obvious.

In the present embodiment, the dummy wiring DML is thus provided onlyaround the pad PD1 where occurrence of a crack becomes obvious, while itis not provided around the pads PD other than the pad PD1. That is, inthe present embodiment, the dummy wiring DML is provided around the padPD1 of minimum necessity where occurrence of a crack in the surfaceprotective film becomes obvious, while it is not provided around thepads PD other than the pad PD1, because occurrence of a crack in thesurface protective film hardly becomes obvious. Thereby, occurrence of acrack in the surface protective film can be suppressed withoutsignificant design modification of the pads PD, according to presentembodiment. When expressed in another way, the distance between therespective pads PD becomes large if the dummy wiring DML is provided foreach of the pads PD, which may cause an increase in the size of thesemiconductor chip CHP. On the other hand, the dummy wiring DML isprovided only around the pad PD1 of minimum necessity where occurrenceof a crack in the surface protective film becomes obvious, in thepresent embodiment, and hence occurrence of a crack in the surfaceprotective film can be suppressed without an increase in the size of thesemiconductor chip CHP. That is, the remarkable effect that thereliability of a semiconductor device can be improved can be acquired,while the miniaturization of the semiconductor device is being kept,according to the present embodiment.

Additionally, in the present embodiment, the level of the surface of thepad PD1 and that of the surface of the dummy wiring DML are the same aseach other, as illustrated in FIG. 12. Thereby, the covering shape ofthe surface protective film PAS covering the end portion of the pad PD1can be made gentle and the thickness of the surface protective film PAScan be made large, in the region D1 illustrated in FIG. 12. That is, inthe case where the level of the surface of the pad PD1 and that of thesurface of the dummy wiring DML are the same as each other, the coveringshape of the surface protective film PAS covering the end portion of thepad PD1 can be made gentler and the thickness of the surface protectivefilm PAS can be made larger in the region D1 than those in the casewhere the levels of the two surfaces are different from each other.Thereby, occurrence of a crack in the surface protective film PAS,covering the end portion of the pad PD1, can be effectively suppressedaccording to the present embodiment.

From the facts described above, it is desirable to form the pad PD1 andthe dummy wiring DML such that the levels of the surfaces thereof arethe same as each other, from the viewpoint that the crack resistance ofthe surface protective film PAS, covering the end portion of the padPD1, is increased by making the covering shape of the surface protectivefilm PAS gentle and making the thickness of the surface protective filmPAS in the region D1 large. However, when the dummy wiring DML isprovided according to the technical ideas of the present embodiment,occurrence of a crack in the surface protective film PAS, covering theend portion of the pad PD1, can be suppressed, even in both of the caseswhere the levels of the surfaces of the pad PD1 and the dummy wiring DMLare different from each other, and where the levels of the surfacesthereof are the same as each other.

Further, it is desirable to make the distance between the pad PD1 andthe dummy wiring DML as small as possible, from the viewpoint that thecrack resistance of the surface protective film PAS is improved. It isbecause, as the distance between the two becomes smaller, a leveldifference, resulting from the thickness of the pad PD1, is more hardlyreflected in the covering shape of the surface protective film PAS. Thatis, as the distance between the two becomes smaller, the covering shapeof the surface protective film PAS becomes duller to a level differenceresulting from the thickness of the pad PD1. That is, by making thedistance between the two small, the covering shape of the surfaceprotective film PAS, covering the end portion of the pad PD1, can bemade gentle and the thickness of the surface protective film PAS can bemade large, in the region D1 illustrated in FIG. 12.

Accordingly, it is desirable to make the levels of the surfaces of thepad PD1 and the dummy wiring DML the same as each other and to make thedistance between the two small, from the viewpoint of increasing thecrack resistance of the surface protective film PAS by making thecovering shape of the surface protective film PAS, covering the endportion of the pad PD1, gentle and making the thickness of the surfaceprotective film PAS in the region D1 large.

In the present embodiment, the covering shape of the surface protectivefilm PAS in the region D1 can be made gentle and the thickness of thesurface protective film PAS in the region D1 can be made large, but thecovering shape of the surface protective film PAS covering the outsideof the dummy wiring DML becomes one in which a level differenceresulting from the thickness of the dummy wiring DML is reflected, asillustrated in FIG. 12. That is, the covering shape of the surfaceprotective film PAS in the region E1 in FIG. 12 becomes precipitous andthe thickness thereof becomes small. Accordingly, occurrence of a crackin the region D1 illustrated in FIG. 12 can be suppressed in the presentembodiment, but there is the possibility that a crack may occur in theregion E1 illustrated in FIG. 12. However, even if a crack occurs in theregion E1 illustrated in FIG. 12 and “aluminum slide” occurs based onthe crack, this “aluminum slide” occurs in the dummy wiring DML. Thatis, even if a crack occurs in the region E1 illustrated in FIG. 12,“aluminum slide” does not occur in the pad PD1 itself, which does notcause any problem. In other words, “aluminum slide” in the pad PD1itself can be suppressed when occurrence of a crack in the region D1illustrated in FIG. 12 can be suppressed, and hence a problem does notoccur even if there is the fear that a crack may occur in the region E1illustrated in FIG. 12. In the present embodiment, it is important tosurely suppress occurrence of a crack in the region D1 illustrated inFIG. 12, because, if a crack occurs in the surface protective filmcovering the end portion of the pad PD1 PAS, namely, occurs in theregion D1 illustrated in FIG. 12, “aluminum slide” may occur in the padD1. In the present embodiment, occurrence of a crack in the region D1illustrated in FIG. 12 can be sufficiently suppressed by providing thedummy wiring DML around the pad PD1, and a problem does not occur evenif there is the fear that a crack may occur in the region E1 illustratedin FIG. 12. However, if the distance between the pad PD1 and the dummywiring DML is small, there is the possibility that: for example, thedummy wiring DML may undergo “aluminum slide” and contact the pad PD1;and the pad PD1, contacted with the dummy wiring DML by the “aluminumslide” of the dummy wiring DML, may also undergo “aluminum slide”.Accordingly, it is also necessary not to make the distance between thepad PD1 and the dummy wiring DML too small, from the viewpoint of surelypreventing the “aluminum slide” of the pad PD1.

From the facts described above, it is desirable to make the distancebetween the pad PD1 and the dummy wiring DML small, from the viewpointof increasing the crack resistance of the surface protective film PAS,covering the end portion of the pad PD1, by making the covering shape ofthe surface protective film PAS gentle and making the thickness of thesurface protective film PAS in the region D1 large. On the other hand,if the distance between the pad PD1 and the dummy wiring DML becomes toosmall, there is the possibility that the pad D1 may undergo “aluminumslide” resulting from the “aluminum slide” of the dummy wiring DML.Accordingly, there is an optimal range of the distance between the padPD1 and the dummy wiring DML, the range which is from a certain distancewhile the distance is preferably made small, from the viewpoint ofavoiding an appearance defect of the pad PD1 by surely preventing the“aluminum slide” of the pad PD1. The distance between the pad PD1 andthe dummy wiring DML can be set, for example, by collecting data onamounts of movement by “aluminum slide”.

<Method of Manufacturing Semiconductor Device> A semiconductor deviceaccording to the present embodiment is configured as described above,and hereinafter a manufacturing method thereof will be described withreference to the drawings.

FIG. 13 is a plan view illustrating a layout configuration of asemiconductor wafer WF. As illustrated in FIG. 13, the semiconductorwafer WF has an approximate disk shape, and has a plurality of chipregions CR in an internal region. Both a semiconductor elementrepresented by a field-effect transistor and a multilayer wiring layerare formed in each of the chip regions CR, and the chip regions CR arepartitioned by scribe regions SCR. In the present embodiment, thesemiconductor wafer (semiconductor substrate) WF, having the chipregions CR each having a rectangular shape and the scribe regions SCRpartitioning the chip regions CR, is provided, as illustrated in FIG.13. In this stage, a semiconductor element represented by a field-effecttransistor is formed in each of the chip regions CR in the semiconductorwafer WF, and the multilayer wiring layer including copper wiring isformed over the semiconductor element by, for example, a damasceneprocess. Subsequent steps will be sequentially described, after a stepof forming a pad in the uppermost layer of the multilayer wiring layerin each of the chip regions CR is first described. This step will bedescribed with attention focused on the integrated circuit region ICR inFIG. 11 corresponding to the sectional view, taken along B-B line inFIG. 9.

As illustrated in FIG. 14, a laminated film, including a barrierconductor film BCF1, an aluminum film AF formed over the barrierconductor film BCF1, and a barrier conductor film BCF2 formed over thealuminum film AF, is first formed over an interlayer insulating film IL.The barrier conductor film BCF1 is formed of a laminated film including,for example, a titanium film and a titanium nitride film, and can beformed by using, for example, a sputtering process. The aluminum film AFis formed of a film including aluminum as a major component, and can beformed by using, for example, a sputtering process. Further, the barrierconductor film BCF2 is formed, for example, of a titanium nitride film,and can be formed by using, for example, a sputtering process.

Subsequently, patterning is performed on the laminated film, includingthe barrier conductor film BCF1, the aluminum film AF, and the barrierconductor film BCF2, by using a photolithography technique and anetching technology, as illustrated in FIG. 15. The pad PD1 and the dummywiring DML can be formed by the patterning of the laminated film. At thetime, the pad PD1 and the dummy wiring DML are formed to be spaced apartfrom each other by a certain distance and formed such that the levels ofthe surfaces of the two are the same as each other.

In this step, the pads PD each having a rectangular shape are formed inthe chip region CR and along a boundary line between the chip region CRand the scribe region SCR (see FIG. 8), and the dummy wiring DML isformed around, of the pads PD, the pad PD1 nearest to the corner CNR ofthe chip region CR (see FIG. 9). As known by referring, for example, toFIG. 9, the dummy wiring DML formed in this step is formed to include:the dummy part DMP1 that is spaced apart from and to be parallel to, ofthe sides that form the pad PD1, the side SD1 nearest to the corner CNRof the chip region CR; and the dummy part DMP 2 that is spaced apartfrom and to be parallel to, of the sides that form the pad PD1, the sideSD2 nearest to the boundary line (corresponding to the edge side ES inFIG. 9).

Subsequently, a silicon oxide film OXF covering the pad PD1 and thedummy wiring DML is formed over the interlayer insulating film IL, asillustrated in FIG. 16. This silicon oxide film OXF can be formed, forexample, by a high-density plasma CVD process. Subsequently, a siliconnitride film SNF is formed over the silicon oxide film OXF, asillustrated in FIG. 17. The silicon nitride film SNF can be formed byusing, for example, a CVD (Chemical Vapor Deposition) process. Thesurface protective film PAS, including the silicon oxide film OXF andthe silicon nitride film SNF, can be thus formed to cover the pad PD1and the dummy wiring DML.

In this case, the dummy wiring DML is formed in a near-field region ofthe pad PD1 in the present embodiment, and hence, even if a leveldifference resulting from the thickness of the pad PD1 is generated, theprecipitousness of the covering shape of the surface protective filmPAS, covering the end portion of the pad PD1, is made gentle and thethickness of the surface protective film PAS in the end portion of thepad PD1 can be made large.

Subsequently, the opening OP for exposing part of the surface of the padPD1 is formed in the surface protective film PAS by using aphotolithography technique and an etching technology, as illustrated inFIG. 18. On the other hand, an opening for exposing the dummy wiring DMLis not formed, and the surface of the dummy wiring DML is maintained ina state of being covered with the surface protective film PAS.Subsequently, the barrier conductor film (titanium nitride film) formedover the surface of the pad PD1 exposed from the opening OP is removedby etching the surface of the exposed pad PD1, as illustrated in FIG.19. Thereby, the aluminum film is exposed from the opening OP.

Thus, the pad PD1 can be formed in the uppermost layer of the multilayerwiring layer. FIG. 20 is a view illustrating a state after the pad PD1is formed, and specifically is a schematic sectional view illustrating aperiphery of a boundary region of the edge side ES. In FIG. 20, the sealring region SRR and the integrated circuit region ICR are formed insidethe scribe region SCR.

Herein, the dummy region DMR is a region integrated with the scriberegion SCR. When the semiconductor wafer is cut into the respectivesemiconductor chips in the later-performed dicing step, part of thescribe region SCR remains inside the edge side ES of the semiconductorchip. In the present embodiment, the remaining region is described asthe dummy region DMR. That is, the region near to the chip edge side ESfrom the seal ring region SRR is referred to as the scribe region SCR(dummy region DMR), while the region away from the seal ring region SRRis referred to as the integrated circuit region ICR, in the presentembodiment.

The dummy pattern DP is formed in the dummy region DMR, and the sealring SRG is formed in the seal ring region SRR. The dummy pattern DP andthe seal ring SRG are formed in the same step as that of forming themultilayer wiring (not illustrated in FIG. 20) in the integrated circuitregion ICR. It is known that, in the integrated circuit region ICR, thepad PD1 and the dummy wiring DML are formed in the uppermost layer.

Subsequently, the following steps will be described with reference to aflowchart. FIG. 21 is a flow chart showing the flow of steps ofmanufacturing a semiconductor device including, for example, a QFPpackage, after the integrated circuit is formed in the semiconductorwafer.

After an integrated circuit is first formed in each of the chip regionsover the semiconductor wafer, the semiconductor wafer is diced along thescribe region (FIG. 21/S101). Thereby, the chip regions are cut intopieces and a semiconductor chip, in which an integrated circuit isformed, can be acquired. After the semiconductor chip is mounted overthe chip mounting part formed in the lead frame (FIG. 21/S102), the padformed in the semiconductor chip and the inner lead are coupled togetherby a wire (FIG. 21/S103). Then, the chip mounting part, thesemiconductor chip, the wire, and the inner lead are sealed with a resin(FIG. 21/S104). After a dam formed in the lead frame is cut (FIG.21/S105), a metal-plated film is formed over the surface of the outerlead exposed from the resin (FIG. 21/S106). Subsequently, a mark isformed over the surface of the resin (FIG. 21/S107), and the outer leadexposed from the resin is shaped (FIG. 21/S108). After a semiconductordevice is thus manufactured, an electrical property inspection isperformed (FIG. 21/S109). A heat cycle test is then performed on thesemiconductor device (FIG. 21/S110), and a product determined to be agood product is shipped as a product.

Herein, in the present embodiment, by providing the dummy wiring DML ina near-field region of the end portion of the pad PD1, as illustrated,for example, in FIG. 12, the precipitousness of the curving shape of thesurface protective film PAS, covering the end portion of the pad PD1,can be made gentle and the thickness of the surface protective film PAScan be made large in the region D1 of the surface protective film PAS,even if a level difference resulting from the thickness of the pad PD1is present in the region D1. Accordingly, stress resistance can beimproved in the region D1 to which the stress from the resin MR, whichseals the surface protective film PAS, is likely to be applied,according to present embodiment. As a result thereof, occurrence of acrack in the surface protective film PAS can be suppressed in the regionD1, according to the present embodiment, and thereby “aluminum slide”,which is likely to occur when a heat cycle test is performed in a statewhere a crack occurs in the surface protective film PAS, can beeffectively suppressed. The fact that the “aluminum slide” can besuppressed means that an appearance defect of the pad PD1 can bereduced, and thereby the reliability of a semiconductor device can beimproved according to the present embodiment.

Effects in Embodiment

Typical effects acquired by the technical ideas of the presentembodiment will be summarized as follows:

(1) In the pad nearest to the corner of a semiconductor chip, theprecipitousness of the surface protective film, covering the end portionof the pad, is made gentle and the thickness of the surface protectivefilm, covering the end portion of the pad, becomes large, and as aresult thereof, the stress from a resin (sealing body) can besuppressed. Thereby, occurrence of a crack in the surface protectivefilm, covering the end portion of the pad nearest to a corner of thesemiconductor chip, can be suppressed according to the presentembodiment.

(2) Because occurrence of a crack in the surface protective film,covering the end portion of the pad nearest to a corner of thesemiconductor chip, can be suppressed according to the presentembodiment, “aluminum slide”, which is likely to occur when a heat cycletest is performed in a state where a crack occurs in the surfaceprotective film, can be effectively suppressed.

(3) Because “aluminum slide” can be suppressed according to the presentembodiment, an appearance defect of the pad can be reduced, and therebythe reliability of a semiconductor device can be improved.

(4) In the present embodiment, occurrence of a crack in the surfaceprotective film, covering the end portion of a pad, can be effectivelyprevented, even if the generations of miniaturization of semiconductorelements and wiring are developed and a level difference resulting fromthe thickness of a pad becomes large. Accordingly, when a generation ofminiaturization is developed and a level difference resulting from thethickness of the pad particularly becomes large, namely, when occurrenceof a crack is likely to become obvious, the availability of thetechnical ideas of the present embodiment is increased.

(5) Further, by making the levels of the surfaces of a pad and dummywiring the same as each other and by making the distance between the padand the dummy wiring within a certain range, the covering shape of thesurface protective film, covering the end portion of the pad, becomesgentle and the thickness of the surface protective film, covering theend portion of the pad, becomes large, and thereby crack resistance canbe further improved in the present embodiment.

<First Variation> FIG. 22 is a schematic view illustrating FirstVariation of the embodiment, the view corresponding to an enlarged viewin which the region C1 in FIG. 8 is enlarged. With reference to FIG. 22,the present First Variation is characterized by the fact that: dummywiring DML is formed by a dummy part DMP1 that is spaced apart from andto be parallel to the side SD1, a dummy part DMP2 that is spaced apartfrom and to be parallel to the side SD2, and a slant part SLP thatcouples the dummy part DMP1 and the dummy part DMP2 together. In thepresent First Variation, the stress, to be applied to a corner of thepad PD1 nearest to the corner CNR of the semiconductor chip CHP, can bereduced by providing the slant part SLP illustrated in FIG. 22, andhence the reliability of a semiconductor device can be further improved.

<Second Variation> FIG. 23 is a schematic view illustrating SecondVariation of the embodiment, the view corresponding to an enlarged viewin which the region C1 in FIG. 8 is enlarged. With reference to FIG. 23,the present Second Variation is the same as the embodiment in that thedummy wiring DML is formed by the dummy part DMP1 and the dummy partDMP2; however, in the present Second Variation, the dummy part DMP1 andthe dummy part DMP2 are formed by a plurality of dot patterns,respectively. Also in this case, the precipitousness of the coveringshape of a surface protective film, covering the end portion of the padnearest to a corner of a semiconductor chip, is made gentle and thethickness of the surface protective film, covering the end portion ofthe pad, becomes large, in the pad similarly to the embodiment. As aresult, the stress from a resin is suppressed, and hence occurrence of acrack in the surface protective film, covering the end portion of thepad nearest to a corner of a semiconductor chip, can be suppressed alsoin the present Second Variation. Thereby, the reliability of asemiconductor device can be improved also in the present SecondVariation.

<Third Variation> FIG. 24 is a schematic view illustrating ThirdVariation of the embodiment, the view corresponding to an enlarged viewin which the region C1 in FIG. 8 is enlarged. With reference to FIG. 24,the present Third Variation has a configuration in which theaforementioned First Variation and Second Variation are combinedtogether. Specifically, the dummy wiring DML is formed by the dummy partDMP1, the dummy part DMP2, and the slant part SLP, and the dummy partDMP1 and the dummy part DMP2 are formed by a plurality of dot patterns,respectively. Also in this case, the precipitousness of the coveringshape of a surface protective film, covering the end portion of a padnearest to a corner of a semiconductor chip, is made gentle and thethickness of the surface protective film, covering the end portion ofthe pad, becomes large, in the pad similarly to the embodiment. As aresult, the stress from a resin is reduced, and hence occurrence of acrack in the surface protective film, covering the end portion of thepad nearest to a corner of a semiconductor chip, can be suppressed alsoin the present Third Variation. Thereby, the reliability of asemiconductor device can be improved also in the present ThirdVariation.

<Fourth Variation> FIG. 25 is a schematic view illustrating FourthVariation of the embodiment, the view corresponding to an enlarged viewin which the region C1 in FIG. 8 is enlarged. With reference to FIG. 25,the present Fourth Variation is the same as First Variation in that thedummy wiring DML is basically formed by the dummy part DMP1, the dummypart DMP2, and the slant part SLP. On the other hand, the present FourthVariation is characterized by the fact that: as illustrated in FIG. 25,the dummy part DMP2, located between a plurality of the pads PD and theedge side ES of the semiconductor chip CHP, extends along the edge sideES of the semiconductor chip CHP. Thereby, occurrence of a crack in asurface protective film, covering the end portions of the pads, can besuppressed not only in the pad PD1 nearest to the corner of thesemiconductor chip CHP, but also in the other pads, according to thepresent Fourth Variation. Thereby, the crack resistance of a surfaceprotective film, covering the end portions of the pads, can be enhancedacross the whole pads PD formed in the semiconductor chip CHP, accordingto the present Fourth Variation, and hence the reliability of asemiconductor device can be further improved.

<Fifth Variation> FIG. 26 is a schematic view illustrating FifthVariation of the embodiment. As known from the comparison of FIG. 12with FIG. 26, the width of the dummy wiring DML in the present FifthVariation illustrated in FIG. 26 is smaller than that of the dummywiring DML in the embodiment illustrated in FIG. 12. Specifically, thewidth (width of the upper base) of the dummy wiring DML in the presentFifth Variation illustrated in FIG. 26 is, for example, approximately 1μm, while that of the dummy wiring DML in the embodiment illustrated inFIG. 12 is, for example, approximately 2 μm. In this case, aconfiguration is achieved in the present Fifth Variation, in which thelevel H2 of the surface protective film PAS, covering the dummy wiringDML, is lower than the level H1 of the surface protective film PAS,covering the pad PD1, while the levels of the surfaces of the pad PD1and the dummy wiring DML are the same as each other. It is because thesilicon oxide film OXF, which forms part of the surface protective filmPAS, is formed by a high-density plasma CVD process. That is, becausethe high-density plasma CVD process is characterized by depositing afilm while etching the film, an etching effect becomes remarkable overthe dummy wiring DML having a small width, while the silicon oxide filmOXF having a large thickness is deposited over the pad PD1 having alarge width, as illustrated in FIG. 26; and the thickness of the siliconoxide film OXF formed over the dummy wiring DML becomes smaller thanthat of the silicon oxide film OXF formed over the pad PD1.

As a result, the precipitousness of the covering shape of the surfaceprotective film PAS, covering the end portion of the pad PD1, is madegentle and the thickness of the surface protective film PAS, coveringthe end portion of the pad PD1, becomes large, also in the present FifthVariation, as illustrated in FIG. 26. As a result, the stress from aresin MR is suppressed, and thereby occurrence of a crack in the surfaceprotective film PAS, covering the end portion of the pad PD1 nearest toa corner of a semiconductor chip, can be suppressed also in the presentFifth Variation. Thereby, the reliability of a semiconductor device canbe improved also in the present Fifth Variation.

The present Fifth Variation further has a peculiar advantage that: notonly the precipitousness of the covering shape is made gentle and thethickness of the surface protective film PAS becomes large in thesurface protective film PAS covering the end portion of the pad PD1, butalso the precipitousness of the covering shape of the surface protectivefilm PAS, covering the end portion of the dummy wiring DML, is madegentle and the thickness thereof becomes large.

Hereinafter, the reason will be described. For example, in theembodiment illustrated in FIG. 12, the thickness of the surfaceprotective film PAS formed over the pad PD1 and that of the surfaceprotective film PAS formed over the dummy wiring DML are almost the sameas each other. Thereby, the precipitousness of the covering shape can bemade gentle and the thickness of the surface protective film PAS can bemade large in the surface protective film PAS covering the end portionof the pad PD1, as illustrated in FIG. 12; however, in the end portionof the dummy wiring DML, the covering shape has a shape in which a leveldifference, resulting from the thickness of the dummy wiring DML, issensitively reflected. That is, the covering shape of the surfaceprotective film PAS in the end portion of the dummy wiring DML becomesprecipitous and the thickness thereof becomes small, as illustrated inFIG. 12. However, if a crack occurs in the surface protective film PAScovering the end portion of the dummy wiring DML illustrated in FIG. 12and thereby “aluminum slide” occurs, the “aluminum slide” occurs only inthe dummy wiring DML, as described in the embodiment. That is, even if acrack occurs in the surface protective film PAS covering the end portionof the dummy wiring DML illustrated in FIG. 12, “aluminum slide” doesnot occur in the pad PD1 itself, which causes no problem. However, asituation in which a crack occurs in the surface protective film PAS isnot desirable, although “aluminum slide” does not occur in the pad PD1itself.

Regarding this point, the thickness of the surface protective film PASformed over the dummy wiring DML becomes smaller than that of thesurface protective film PAS formed over the pad PD1, in the presentFifth Variation illustrated, for example, in FIG. 26. From this,according to the present Fifth Variation, the precipitousness of thecovering shape can be made gentle and the thickness of the surfaceprotective film PAS can be made large in the surface protective film PAScovering the end portion of the pad PD1, and the precipitousness of thecovering shape can be made gentle and the thickness of the surfaceprotective film PAS can be made large also in the surface protectivefilm PAS covering the end portion of the dummy wiring DML, asillustrated in FIG. 26. That is, in the present Fifth Variation, notonly occurrence of a crack in the surface protective film PAS coveringthe end portion of the pad PD1, but also occurrence of a crack in thesurface protective film PAS covering the end portion of the dummy wiringDML can be suppressed. Accordingly, it can be said that the availabilityof the technical ideas of the present Fifth Variation is high from theviewpoint of improving the reliability of a semiconductor device interms that occurrence of a crack in any location of the surfaceprotective film PAS can be suppressed.

The invention made by the present inventors has been specificallydescribed above based on its preferred embodiments, but it is needlessto say that the invention should not be limited to the embodiments andmay be modified variously within a range not departing from the gistthereof.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip having a rectangular shape, wherein the semiconductorchip includes: (a) a plurality of pads arranged along an edge side ofthe semiconductor chip; and (b) dummy wiring provided around, of thepads, a first pad that is arranged at a position nearest to a corner ofthe semiconductor chip and has a rectangular shape, and wherein thedummy wiring includes: (b1) a first dummy part provided to be spacedapart from and to be parallel to a first side nearest to the corner, ofa plurality of sides that form the first pad; and (b2) a second dummypart provided to be spaced apart from and to be parallel to a secondside nearest to the edge side of the semiconductor chip of the sidesthat form the first pad.
 2. The semiconductor device according to claim1, wherein a semiconductor element is formed in the semiconductor chip,and wherein the dummy wiring is not electrically coupled to thesemiconductor element, so that the dummy wiring does not function aswiring.
 3. The semiconductor device according to claim 2, wherein apotential of the dummy wiring is in a floating state.
 4. Thesemiconductor device according to claim 1, wherein the dummy wiring isformed in the same layer as that of the first pad.
 5. The semiconductordevice according to claim 4, wherein a level of a surface of the dummywiring is the same as that of a surface of the first pad.
 6. Thesemiconductor device according to claim 1, wherein a seal ring, forsuppressing a foreign substance from entering inside of thesemiconductor chip, is formed between the second dummy part and the edgeside of the semiconductor chip.
 7. The semiconductor device according toclaim 6, wherein a semiconductor element is formed in the semiconductorchip, and wherein wiring to be electrically coupled to the semiconductorelement is not provided between the first pad and the seal ring.
 8. Thesemiconductor device according to claim 1, wherein the first dummy partand the second dummy part are formed integrally with each other.
 9. Thesemiconductor device according to claim 8, wherein the first dummy partand the second dummy part are coupled together by a slant part.
 10. Thesemiconductor device according to claim 8, wherein, while locatedbetween the pads and the edge side of the semiconductor chip, the seconddummy part extends along the edge side of the semiconductor chip. 11.The semiconductor device according to claim 1, wherein the first dummypart is formed by a plurality of dot patterns, and wherein the seconddummy part is formed by a plurality of dot patterns.
 12. Thesemiconductor device according to claim 11, wherein, while locatedbetween the pads and the edge side of the semiconductor chip, the seconddummy part extends along the edge side of the semiconductor chip. 13.The semiconductor device according to claim 1, wherein a surfaceprotective film is formed to cover the pads and the dummy wiring, andwherein an opening, for exposing part of a surface of each of the pads,is formed in the surface protective film.
 14. The semiconductor deviceaccording to claim 13, wherein a level of the surface protective filmcovering the dummy wiring is lower than that of the surface protectivefilm covering the first pad, while a level of a surface of the first padis the same as that of a surface of the dummy wiring.
 15. Thesemiconductor device according to claim 13, wherein the semiconductorchip is sealed by a sealing body including a resin.
 16. A method ofmanufacturing a semiconductor device comprising the steps of: (a)providing a semiconductor substrate including a chip region having arectangular shape and a scribe region partitioning the chip region; and(b) forming a plurality of pads each having a rectangular shape along aboundary line between the chip region and the scribe region, and formingdummy wiring around, of the pads, a first pad nearest to a corner of thechip region, wherein the dummy wiring formed in the step (b) includes: afirst dummy part provided to be spaced apart from and to be parallel toa first side nearest to a corner of the chip region, of a plurality ofsides that form the first pad; and a second dummy part provided to bespaced apart from and to be parallel to a second side nearest to theboundary line, of the sides that form the first pad.
 17. The method ofmanufacturing a semiconductor device according to claim 16, comprisingthe steps of: (c) forming a surface protective film covering the padsand the dummy wiring; (d) forming an opening for exposing part of asurface of each of the pads in the surface protective film; (e) afterthe step (d), acquiring a semiconductor chip by dicing the semiconductorsubstrate along the scribe region; (f) after the step (e), coupling awire to the surface of each of the pads exposed from the opening; and(g) after the step (f), sealing the semiconductor chip.
 18. The methodof manufacturing a semiconductor device according to claim 17,comprising the step of: after the step (g), performing a heat cycletest.
 19. The method of manufacturing a semiconductor device accordingto claim 17, wherein the step (c) includes the steps of: (c1) forming asilicon oxide film so as to cover the pads and the dummy wiring; and(c2) forming a silicon nitride film over the silicon oxide film.
 20. Themethod of manufacturing a semiconductor device according to claim 19,wherein the step (c1) is performed by using a high-density plasma CVDprocess.